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RM0008
7.2.5
Connectivity line devices: reset and clock control (RCC)
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency of
32.768 kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup
domain control register (RCC_BDCR) . The external clock signal (square, sinus or triangle)
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left Hi-Z. See Figure 12 .
LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR) .
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR) .
LSI calibration
The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to
have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for
these peripherals) with an acceptable accuracy.
This calibration is performed by measuring the LSI clock frequency with respect to TIM5
input clock (TIM5CLK). According to this measurement done at the precision of the HSE
oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an
accurate time base or can compute accurate IWDG timeout.
Use the following procedure to calibrate the LSI:
1.
2.
3.
4.
Enable TIM5 timer and configure channel4 in input capture mode
Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock
internally to TIM5 channel4 input capture for calibration purpose.
Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or
interrupt.
Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending
on the desired time base and/or to compute the IWDG timeout.
7.2.6
System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the Clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as system clock.
Doc ID 13902 Rev 9
111/995
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